1. Field of the Invention
The present invention relates to a nonvolatile memory device and a method of forming a nonvolatile memory device.
2. Description of Related Art
As electrical devices become miniaturized and portable, the need for nonvolatile memory devices becomes even greater. In general, nonvolatile memory devices store information without having to supply electrical power. For example, a nonvolatile memory device such as a flash memory employs a floating gate to store information. The flash memory changes information stored in a cell transistor, for example, by performing program and erase operations. The program and erase operations generally require large voltage differences (greater than about 10 volts). Accordingly, the flash memory includes a plurality of pumping circuits to establish the necessary large voltage difference. As the number of pumping circuits needed on the nonvolatile memory device rise, the integrity of a semiconductor device product containing the nonvolatile memory device is reduced, and cost of the product increases. In addition, the flash memory has a technical disadvantage, in that the transistor employing the flash memory (and interconnections thereto) should be designed so as to avoid breakdown due to the large voltage difference.
As an alternative to flash memory devices, a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory device has recently been studied and proposed. Generally, the SONOS type nonvolatile memory device includes sequentially stacked layers, e.g., an oxide layer, a nitride layer, another oxide layer and a polysilicon layer that are sequentially stacked. The nitride layer is sandwiched between the oxide layers and used as an electric charge trapping medium. Information is stored in the charge trapping medium of the SONOS type nonvolatile memory device. In other words, the nitride layer performs a function similar to the function of a floating gate in the flash memory device.
In order to provide a highly integrated semiconductor device, a SONOS type nonvolatile memory may be included in a structure where two adjoining cells, such as memory transistor cells, share a common source line. In this case, the two cells may have different channel lengths. Asymmetrical channel lengths may occur in what is referred to as a ‘split-gate’ type FLASH memory, for example.
FIGS. 9 and 10 are perspective views illustrating a prior art method for fabricating a SONOS type nonvolatile memory device. Referring to FIGS. 9 and 10, a lower oxide layer 20 is formed on the semiconductor substrate 10, and a charge storage pattern 30 is formed on the lower oxide layer 20. The charge storage pattern 30 is formed of an insulating layer (such as a silicon nitride layer, for example) having a sufficient number of charge trap sites. Then, an upper oxide layer 40 is formed on the charge storage pattern 30 so as to conform to the charge storage pattern 30.
A gate conductive layer is formed over an entire surface of the semiconductor substrate 10 and the upper oxide layer 40. The gate conductive layer is then patterned to form gate patterns 50 crossing over the charge storage pattern 30. An ion implantation process is performed using the gate patterns 50 as a mask to form an impurity region 60 in the semiconductor substrate 10. The impurity regions 60 are used as a source and/or a drain of a memory cell transistor.
The gate patterns 50 are typically formed by a conventional photolithographic process so as to be misaligned to the charge storage pattern 30. As shown in FIG. 10, channel lengths I1 and I2 of the adjoining two cell transistors may be changed by the misalignment between the gate pattern 50 and the charge storage pattern 30 (i.e., I1≠I2).
The asymmetry due to the misalignment may cause what is known as ‘periodical irregularities’ to appear at interconnections between one or more cell transistors and the one source line. These periodical irregularities are commonly known as ‘even-odd failures’ and may adversely affect cell transistor performance.